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6001 / GAL6001B-30LP/ GAL6001B fpla generic array logic
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HIGH PERFORMANCE E2CMOS® TECHNOLOGY
30ns Maximum Propagation Delay
12ns Maximum Clock to Output Delay
UltraMOS® Advanced CMOS Technology
High Speed Electrical Erasure (<100ms)
UNPRECEDENTED FUNCTIONAL DENSITY
78 x 64 x 36 FPLA Architecture
20 Input and I/O Logic Macrocells
Asynchronous or Synchronous Clocking
Separate State Register and Input Clock Pins
Functional Superset of Existing 24-pin PAL® and FPLA Devices
Multiple PLD Device Integration
2CMOS technology, Lattice Semiconductor has produced a next-generation programmable logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a high degree of functional integration and flexibility in a 24-pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells (OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In addition, there are 10 Input Logic Macrocells (ILMC) and 10 I/O Logic Macrocells (IOLMC). Two clock inputs are provided for independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time, coupled with E
2CMOS reprogrammable cells, enable 100% AC, DC, programmability, and functionality testing of each GAL6001 during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
